Download Current Trends in Hardware Verification and Automated by Avra Cohn (auth.), Graham Birtwistle, P. A. Subrahmanyam PDF

By Avra Cohn (auth.), Graham Birtwistle, P. A. Subrahmanyam (eds.)

This file describes the partly accomplished correctness evidence of the Viper 'block model'. Viper [7,8,9,11,23] is a microprocessor designed by means of W. J. Cullyer, C. Pygott and J. Kershaw on the Royal indications and Radar institution in Malvern, England, (henceforth 'RSRE') to be used in safety-critical purposes corresponding to civil aviation and nuclear strength plant regulate. it truly is at present discovering makes use of in components resembling the de­ ployment of guns from tactical airplane. To help safety-critical purposes, Viper has a particulary easy layout approximately which it's fairly effortless to cause utilizing present ideas and versions. The designers, who deserve a lot credits for the advertising of formal tools, meant from the beginning that Viper be officially proven. Their notion was once to version Viper in a chain of decreasingly summary degrees, each one of which targeting a few point ofthe layout, akin to the circulate ofcontrol, the processingofinstructions, and so forth. that's, each one version will be a specification of the following (less summary) version, and an implementation of the former version (if any). The verification attempt could then be simplified by means of being established in keeping with the series of abstraction degrees. those types (or degrees) of description have been characterised by way of the layout group. the 1st degrees, and a part of the 3rd, have been written through them in a logical language amenable to reasoning and proof.

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Additional resources for Current Trends in Hardware Verification and Automated Theorem Proving

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1\ (pause_sig(n+'1l = 1\ (reply_sig(n+1l = 1\ (reset_sig(n+l) = 1\ (e_iobar_sig n = 1\ (e_data_out_sig n = 1\ (e_address_sig n =. 1\ (e_strobebar_sig n = 1\ (e_vritebar_sig n = ... sig(n+1l = ... sig n = 1\ (minor_sig(n+1) :Il MINOR_ABBR (minor ,major ,pause, reply ,carryused,reset ,stop, inst. bflag, count ,error) 1\ (major_sig(n+1l = MAJOR_ABBR (major ,stop, inst, bflag,count reset ,error ,minor ,pause, reply, carryused) /\ (bflag_sig(n+ll = BFLAG_ABBR (stop,stmplx ,bmplx, inst ,major ,minor ,pause, reply ,carryused,clkenbp, areg,xreg, yreg,preg.

Whether the value of the register source is less than the value of the memory source), the result of the comparison is EL 32 (BITS34 (VORD34 «VAL33(SIGIEXT(REGSELECT_ABBR(areg,xreg, yreg,preg, ram»» «VAL33(SIGIEXT(MEM_ABBR(ram,preg») = 0) => 0 I (VAL33(IOT33(SIGIEXT(MEM_ABBR(ram,preg»») + 1»» + That is, the value of the sign-extended source is added to 0 if the value of the signextended memory is 0, and to the incremented value of the negated sign-extended memory value otherwise; and the thirty-second bit of that 34-bit sum is the result.

S trobeaddr_s ig. rsel_sig. outt_sig out2_sig out3_sig out4_sig outS_sig out6_sig out7 _sig. REGISTERS_COIlB (extdatabar_sig, aout bar_s ig, C lkenb_s ig, regs tro be_s ig, s trobeaddr_ s ig. Ireg_sig, yreg_sig,preg_sig, treg_sig. addr_sig, inst_sig. out1_sig, out2_sig. out4_sig, outS_sig. out6_sig, out7_sig) /\ LATCR32(outl_sig,aros-sig) 1\ LATCR32(out2_sig, xrog_sig) 1\ LATCH32(out3_sig, yrog_sig) 1\ LATCH20(out4_sig,prog_sig) 1\ LATCH32(out5_sig, trog_sig) 1\ LATCR20(out6_sig, addr_sig) 1\ LATCR12(out7_sig,inat_sig) 1\ REGS ELECT _CO"B(areg_sig.

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